The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device which is capable of removing fixed pattern noise of pixels and fixed pattern noise caused by a shading that is generated by a horizontal scanning circuit. More specifically, the present invention is concerned with an X-Y addressable solid-state imaging device which is capable of reading pixel information, pixel by pixel, depending on a signal charge which has been generated by each pixel through photoelectric conversion.
To meet demands for higher-resolution solid-state imaging devices, there have been developed in recent years amplification-type solid-state imaging devices which are free of smearing and capable of realizing fine pixels, for use in place of CCD solid-state imaging devices. The amplification-type solid-state imaging devices have pixels comprising active devices of MOS structure (MOS transistors) for enabling the pixels to amplify light signals, and are arranged to read charges stored in the pixels by photoelectric conversion as signals that are current-modulated by the transistors.
Since the pixels of the amplification-type solid-state imaging devices comprise active devices (MOS transistors) variations of the active devices are reflected in video signals generated by the amplification-type solid-state imaging devices. Since such variations of the active devices have fixed values associated with the respective pixels, they appear as fixed pattern noise (hereinafter also referred to as "FPN") in the reproduced image.
The FPN is caused not by variations in pixel sensitivity to incident light, but by threshold variations of the pixels which are added to signals depending on incident light.
Removal of FPN will be described below with respect to a conventional amplification-type solid-state imaging device shown in FIG. 1 of the accompanying drawings.
As shown in FIG. 1, the amplification-type solid-state imaging device, generally denoted by 1, has photodetectors 2 each serving as a unit pixel (cell), the photodetectors 2 comprising pixel MOS transistors, respectively, which are arranged in a matrix of rows and columns. The pixel MOS transistors 2 in the rows have control electrodes or gates connected to vertical selection lines 4 associated with the respective rows. The amplification-type solid-state imaging device 1 also has a vertical scanning circuit 3 for applying a vertical scanning signal, i.e., vertical scanning pulses .phi.V (.phi.V.sub.1, . . . , .phi.V.sub.m, .phi.V.sub.m+1, . . . ), successively to the vertical selection lines 4.
The pixel MOS transistors 2 in the columns have respective sources, i.e., one type of principal electrodes thereof, connected to vertical signal lines 5 associated with the respective columns, and also have respective drains, i.e., the other type of principal electrodes thereof, connected to a power supply V.sub.D.
Each of the vertical signal lines 5 is connected through a first operation MOS switch 7 to a first load capacitance element 8 for holding a signal voltage (charge). The junction between the first operation MOS switch 7 and the first load capacitance element 8 is connected through a first horizontal MOS switch 9 to a first horizontal signal line 10. Each of the vertical signal lines 5 is also connected through a second operation MOS switch 7' to a second load capacitance element 8'. The junction between the second operation MOS switch 7' and the second load capacitance element 81 is connected through a second horizontal MOS switch 9' to a second horizontal signal line 11. The first and second load capacitance elements 8, 8' are connected between the vertical signal lines 5 and ground.
A first operation pulse .phi..sub.OPS is applied to the gate of each of the first operation MOS switches 7, and a second operation pulse .phi..sub.OPN is applied to the gate of each of the second operation MOS switches 7'. The first and second horizontal MOS switches 9, 9' have respective gates connected in common to a horizontal shift register 12, which applies a horizontal scanning signal, i.e., successive horizontal scanning pulses .phi.H (.phi.H.sub.1, . . . , .phi.H.sub.n, .phi.H.sub.n+1, . . . ), to the first and second horizontal MOS switches 9, 9'.
Resetting MOS switches (not shown) for resetting the first and second load capacitance elements 8, 8' and the vertical signal lines 5 to an initial voltage are connected to the vertical signal lines 5 on the side of the first load capacitance elements 8 in which the first operation MOS switches 7 are present. The resetting MOS switches have respective sources connected to the vertical signal lines 5, respective drains supplied with a resetting bias voltage V.sub.RB, and respective gates supplied with a resetting pulse .phi..sub.VRST.
The first operation MOS switches 7, the first load capacitance elements 8, and the first horizontal MOS switches 9 jointly make up a first signal holding circuit 19 for holding signal voltages (charges) of pixels before the pixels are reset. The second operation MOS switches 7', the second load capacitance elements 8', and the second horizontal MOS switches 9' jointly make up a second signal holding circuit 20 for holding signals from pixels after the pixels are reset, i.e., noise signals.
The first and second horizontal signal lines 10, 11 have respective output ends connected to respective first and second charge detecting circuits 16, 16' each comprising an operational amplifier 13 in the form of an inverting amplifier, e.g., a differential amplifier, a detection capacitance element 14, and a resetting switch 15. Specifically, the first and second horizontal signal lines 10, 11 are connected to respective inverting input terminals of the operational amplifiers 13 of the respective charge detecting circuits 16, 16'. A predetermined bias voltage V.sub.B is applied to the noninverting input terminals of the operational amplifiers 13. The bias voltage V.sub.B serves to determine a potential of the first and second horizontal signal lines 10, 11. In each of the first and second charge detecting circuits 16, 16', the detection capacitance element 14 is connected across the operational amplifier 13, i.e., between the inverting input terminal and output terminal of the operational amplifier 13, and the resetting switch 15 is connected across the detection capacitance element 14 for resetting the first and second horizontal signal lines 10, 11 and the detection capacitance element 14. The resetting switch 15 has a gate to which a resetting pulse .phi..sub.R will be applied.
The first and second charge detecting circuits 16, 16' have respective output terminals, i.e., a signal output terminal t.sub.S and a noise output terminal t.sub.N, which are connected to a differential amplifier 17 which subtracts signals at the signal output terminal t.sub.S and the noise output terminal t.sub.N one from the other.
The amplification-type solid-state imaging device 1 operates as follows: A signal outputted from the principal electrodes of each of the pixel MOS transistors 2 depending on a signal charge converted from incident light and stored therein (i.e., a signal before the pixel is reset=a signal converted from incident light+fixed pattern noise (FPN) of the pixel) is transferred from the vertical signal line 5 through the first operation MOS switch 7 to the first load capacitance element 8, which holds (stores) the supplied signal.
After each of the pixel MOS transistors 2 is reset, a signal outputted from the principal electrodes of the pixel MOS transistor 2 (i.e., a signal after the pixel is reset=only fixed pattern noise (FPN) of the pixel) is transferred from the vertical signal line 5 through the second operation MOS switch 7' to the second load capacitance element 8', which holds (stores) the supplied signal.
When the first and second horizontal MOS switches 9, 9' are rendered conductive, the signal before the pixel is reset, which is stored in the first load capacitance element 8, and the signal after the pixel is reset, which is stored in the second load capacitance element 8', are outputted respectively through the first and second horizontal signal lines 10, 11 and the first and second charge detecting circuits 16, 16' to the respective output terminals t.sub.S. t.sub.N, from which the signals are supplied to the differential amplifier 17. The differential amplifier 17 subtracts the signal after the pixel is reset from the signal before the pixel is reset, thereby removing the FPN, and outputs the signal free of FPN to an output terminal t.sub.out.
However, the amplification-type solid-state imaging device 1 suffers disadvantageous described below. The amplification-type solid-state imaging device 1 needs two output circuits for outputting signals before and after the pixels are reset, i.e., the first and second charge detecting circuits 16, 16'. Furthermore, while the amplification-type solid-state imaging device 1 can remove FPN generated by the pixel MOS transistors 2, if the two signals before and after the pixels are reset contain shadings of different magnitudes due to a slight difference between the layouts of the first and second signal holding circuits 19, 20, then a shading remains unremoved from the signal outputted to the output terminal t.sub.out even when the signals before and after the pixels are reset are subtracted one from the other by the differential amplifier 17.
More specifically, the layout of the first operation MOS switches 7, the first load capacitance elements 8, and the first horizontal MOS switches 9, and the layout of the second operation MOS switches 7', the second load capacitance elements 8', and the second horizontal MOS switches 9' differ positionally from each other, and the operation pulses .phi..sub.OPS, .phi..sub.OPN and the horizontal scanning pulses .phi.H.sub.n, .phi.H.sub.n+1 are not exactly equivalent to each other. As a consequence, a signal produced at the output terminal t.sub.S (a signal converted from incident light+fixed pattern noise (FPN) of the pixels) and a signal produced at the output terminal t.sub.N (only fixed pattern noise (FPN) of the pixels) suffer different shadings as shown in FIG. 2 of the accompanying drawings, with the result that the output signal at the output terminal tout, from which FPN is canceled, still contains a shading.
Therefore, the above amplification-type solid-state imaging device in which the signals produced before and after the pixels are reset are outputted from the respective separate circuits and then subtracted one from the other to remove FPN of the pixels from the output signal has been problematic because the output signal from which FPN is canceled tends to contain a shading generated by the horizontal scanning circuit.
The amplification-type solid-state imaging devices, which are one type of X-Y addressable solid-state imaging device, employ active devices of MOS structure (MOS transistors) as pixels to give the pixels an amplifying capability. As described above, variations of the active devices are reflected in video signals generated by the amplification-type solid-state imaging devices, and have fixed values associated with the respective pixels. Therefore, the variations appear as fixed pattern noise (FPN) in the produced image. The FPN is caused by threshold variations of the pixels which are added to signals depending on incident light, rather than by variations in pixel sensitivity to incident light.
FIG. 3 of the accompanying drawings show another amplification-type solid-state imaging device arranged to remove FPN caused by characteristic variations of the pixels. As shown in FIG. 3, the amplification-type solid-state imaging device has a pixel area 101 comprising a matrix of pixels arrayed in rows and columns, a vertical scanning circuit 102 disposed on one side of the pixel area 101 for successively selecting the rows of pixels in the pixel area 101, and noise and signal horizontal scanning circuits 103, 104 disposed upwardly and downwardly, respectively, of the pixel area 101 for successively selecting the columns of pixels in the pixel area 101.
Signals are read from the pixels as follows: Signals (containing noise components) of pixels belonging to a row selected by the vertical scanning circuit 102 are successively read in a horizontal scanning cycle by the signal horizontal scanning circuit 104. After the pixels are reset, the noise components of the pixels of the same row are successively read in a horizontal scanning cycle by the noise horizontal scanning circuit 103. Thereafter, the noise components are subtracted from the signals by an external signal processing circuit (not shown in FIG. 3), thereby canceling fixed pattern noise contained in the signals.
In the amplification-type solid-state imaging device shown in FIG. 3, the noise and signal horizontal scanning circuits 103, 104 are disposed upwardly and downwardly, respectively, of the pixel area 101, and signals and noise components of the pixels are read through respective signal reading circuits separate from each other. While the amplification-type solid-state imaging device is able to remove fixed pattern noise caused by characteristic variations of the active devices of the pixels, it fails to remove noise components due to characteristic variations of devices of the signal reading circuits and the horizontal scanning circuits 103, 104. Such noise components which remain unremoved appear as vertical stripes of fixed pattern noise in the reproduced image.